Digital circuits often include multiple clocks that must have a specific frequency relationship. In order to prevent drift of operation in one clock domain with respect to another, that relationship is sometimes very precise. If the relationship between the frequencies is integral, a simple clock divider may be used. However, if the relationship is non-integral, more involved circuitry is used.
For example, in audio/visual systems there may be an audio decoder that runs at one clock speed and a video decoder that runs at another speed. As a result, the audio decoder and the video decoder need to each run in their own clock domain, but they have to have a specific relationship to each other that remains stable over time. The reason being, if, for example, a DVD is being played, there must be lip sync, where the sound coming out should be lined up on a frame-by-frame basis with the video. Otherwise, the audio and video drift apart over time and the sound gets a few seconds behind the video.
In the simplest of cases, there may be an integral relationship between the audio decoder and video decoder clocks. For example, the video clock may be exactly three times as fast as the audio clock, in which case a simple digital clock divider is used to have the audio played at one-third the frequency of the video. A more likely situation is where the clocks have a non-integral relationship. For example, one clock may run 5/9 as fast as another clock.
Typically when 2 clocks must have a specific non-integral frequency relationship they are created using one or two phase locked loops (PLLs). PLLs have the characteristic that they enable the generation of output clocks at any reasonable rational ratio of output to the input. One method used to achieve the non-integral relationship is by generating one clock using a PLL driven off of another clock generated by a PLL. With this method, an input clock and a first PLL are used to generate a first (video) clock. The generated first clock is then input into a second PLL to generate a second (audio) clock.
Another method used to achieve the non-integral relationship is by using two PLLs to generate two clocks using the same input clock. Using this method, an input clock is used with one PLL to generate a first (video) clock. The same input clock is also used with a second PLL to generate a second (audio) clock.
Use of PLLs introduces analog circuits into the design. Relative to digital circuits, analog circuits generally are more difficult to make reliable due to their greater noise susceptibility and sensitivity to component processing variations. Additionally, PLLs are generally an expensive solution in terms of ASIC die area, or component cost on a board, relative to a fully digital solution. Furthermore, PLLs usually come with a variety of restrictions in their allowed programming values (e.g. minimum/maximum internal oscillator frequencies, min/max feedback/input/output divider values). Because PLLs require special components (e.g. capacitors), extra chip fabrication steps (extra cost/time/complexity) may be required relative to the baseline process typically used for digital circuits. PLLs also have many restrictions since they have internal oscillators that have to run within certain ranges and they have input and output dividers that can only operate in certain ranges.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.